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Physical Design Considerations for Embedded Memory Integration

Posted by on in Physical Design
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b2ap3_thumbnail_cedronics-physical-design-250x250.gifWhen designing a product that operates off of a small battery, low power consumption is extremely critical. A well-designed power system can be a key differentiator for a competitive low-power product. Designing an ultra-low-power system, on the other hand, can be a highly complex undertaking. A design team needs to balance and integrate a variety of low-power design approaches and techniques to achieve their goals. Using a combination of multiple power domains and operating voltages, along with thorough statistical analysis, a low power product can be designed to provide a competitive advantage.

Any company that develops products that operate off a small battery can benefit from considering well-integrated, physical design practices for low power consumption design targets. Wireless sensors, mesh networks, wearables, Bluetooth devices, Internet of Thing (IoT) devices, hearing aids, mobile phone audio/video processing capabilities, tablets and headsets all require an optimized approach to achieve ultra-low power.

So, what is it that these ultra-low-power products need? Often, a minimum clock rate will be used meet performance goals. Higher threshold voltage (VT) devices may be used to minimize leakage. Perhaps multiple clock domains, multiple power domains and/or multiple operating voltages will be part of the low-power design solution. Lower operating and standby voltages lead to much lower overall power consumption; however, multiple power domains also result in a complex SOC (system on a chip) power structure.

As part of the overall SOC power system solution, there are a number of considerations for the embedded memory when using multiple power domains. The periphery voltage will use the same power supply as the logic to ensure valid timing closure, and this supply must be as low as possible to achieve minimum dynamic power. The bit cell voltage, or core voltage, on the other hand, will be dictated by the requirements of the foundry‚Äôs bit cell for stability and reliability. This is VDDmin. The bit cell voltage does not track the low dynamic power requirements needed for logic. For these two different voltage domains, a built-in level shift is required from the periphery voltage to the core voltage.

Finally, the embedded memory will have a retention mode, or standby power. This is the minimum current required to retain the embedded memory (SRAM) contents. In this case, the periphery will be powered off, and there may be multiple power supplies for multiple memory arrays within each embedded memory instance. Using multiple power supplies for the memory arrays allows retention for the minimum necessary address range in the memory during a standby mode.

In the following diagram, as an example, is a custom, low-power embedded memory instance with five power supplies: VDD to power the periphery, and VDM0, VDM1, VDM2 and VDM3 to each power one quarter of the memory array core.

Mobile Semi Image 1

Multiple operating and standby voltages may, therefore, be a key design approach used to reach low power targets. For high-performance processing needs, a standard or overdrive voltage of 1.0-1.2V may be required. Lower power processing functions, however, will place smaller demands on the CPU - perhaps in watching and waiting activities - and the operating voltage may be lowered to 0.6-0.9V. Further, to conserve power, a standby mode can be used to power off everything except for the minimum amount of data needed, as defined by the system state. For standby mode, the voltage may then be lowered to 0.4-0.9V.

With multiple power domains and multiple operating voltages, you can see that the SOC soon becomes a complex system of power switches with a very complex physical power structure. This requires a good power plan, but the final power plan is often decided too late in the design phase. Then, performing power analysis late in the design can dictate changes or lead to needing more power domains. This leaves insufficient time for the physical design of the power system. Problems are identified late in the design phase. By this point, bringing up the necessary power tools - if they are even available - is impractical. Power planning problems, therefore, should be solved in simulation, not silicon.

Even in the case where the design schedule adequately provides for power analysis, several things can go wrong with both timing verification and power rail verification for complex power designs. Dynamic power rail analysis has an associated impact on path timing.  Timing does not track across multiple power domains, and increased power system complexity also increases the degrees of freedom in paths. This cannot be easily analyzed. Peak current demands may also not be accounted for during verification. This may especially be a concern for zinc-air batteries. Finally, statistical variations in devices and wiring capacitances increase the uncertainties in both timing and power analysis.

So, how do you achieve an ultra-low-power, competitive power system solution? First of all, perform thorough statistical analysis of power and current waveforms, incorporating the effects of dynamic power variation. Secondly, use power analysis EDA tools. Dynamic power analysis results needs to be linked to timing. Review power analysis results to ensure sufficient decoupling capacitance has been used. Any IP you integrate into the SOC needs to supply accurate and detailed information for the EDA tool suite. For example, there must be complete power models, including current wave forms (i.e. CCS or ECSM), and there must be UPF or CPF power models. Plan ahead for the EDA tool flow, and ensure that the plan ensures that all of the IP include adequate models.

Power system success is achieved by employing a variety of design techniques, using good analysis tools, and incorporating detailed and accurate IP models. When applying these low power design and analysis techniques to a DSP design that included two power domains, two operating voltages, as well as a standby mode,  a 3x reduction in dynamic power and a 10x reduction of leakage resulted. Additionally, no loss in performance resulted as the supply was increased when necessary to achieve operating performance targets. Using a combination of multiple power domains and operating voltages, along with thorough statistical analysis, a well-designed power system can result in a competitive low power product.

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