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b2ap3_thumbnail_download.gifAbstract:
This paper will explain how new ASSP ventures face challenges that can derail success of a product even before the first device is sold, including market entry barriers such as time to market pressures, limited human and financial resources, and increased design complexity. In order to overcome these hurdles, these companies must consider a business model that enables a cost-effective design methodology flexible enough to allow changes within this unstable market environment. ASSP prototyping with FPGAs and then migrating to structured ASICs for production provides the best answer to this critical dilemma. 

Introduction
System companies looking to implement new ideas in integrated circuits are faced with several challenges today, including higher upfront costs, increased risk due to higher design complexity and shrinking market windows. Traditional technology choices have included cell-based application specific integrated circuits (ASICs), application specific standard products (ASSPs), field programmable gate arrays (FPGAs) or microprocessors and digital signal processors (DSPs). While each of these technologies has its own pros and cons, standard cell ASICs have historically been the best option in the production phase of a design providing the lowest unit production costs and lowest power consumption for system design. 

However, designing a standard cell ASIC at the 90-nm node today is both an expensive and risky development proposition. Non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts such as layout and verification, continue to rise as designs migrate to manufacturing technologies using smaller process geometries. Total development costs of a single complex, high-density standard cell ASIC at the 90-nm process node, can be in the $20-30 million range (see Figure 1). 


Figure 1. Increasing Development Costs


Getting a device functioning correctly the first time is imperative to avoid additional costs and delays associated with re-spinning the ASIC. Simulation, verification and validation of a design must be performed to ensure that the ASIC design is correct before tape-out and after silicon has been received. Re-spins pose serious problems, not only increasing costs of engineering and mask-sets but also from a lost market opportunity perspective. According to International Business Strategies, being 3 to 12 months late to market with a product can result in a potential sales loss ranging from 27 to 91 percent, respectively (see Table 1).

Time-To-Market Potential Sales Achieved
First-To-Market 100%
3 Months Late 73%
6 Months Late 53%
9 Months Late 32%
12 Months Late 9%

Table 1. Time-to-market matters

These increased costs and high design risks are forcing designers to do a more thorough return on investment (ROI) analysis to justify these expenses, which usually demands significant unit volumes be shipped to ensure an acceptable return. For example, if a company spends 20 percent of its estimated revenue on research and development for a 90-nm, high-density standard cell ASIC, say $30 million, device revenue would have to hit $150 million per year. A single device rarely has more than a 10 percent market share, therefore a total market size of $1.5 billion would be needed to ensure an acceptable ROI. 

The following example illustrates the magnitude of this volume requirement. Assuming a chip has an average selling price of $10, this device would need a run rate of 15 million units per year to generate $150 million in revenue. With the exception of highly popular digital consumer products such as MP3 players or certain gaming consoles, very few markets approach this size. 

Design Alternatives Provide Lower-Risk and Smaller Upfront Costs

Historically, FPGAs have been perceived as cost prohibitive, and performance and density limited when compared to standard cell ASICs. However, FPGAs today are manufactured on leading edge 90-nm processes that have allowed them to meet a majority of new ASIC or ASSP design start requirements due to significant improvements in performance, density and cost. In fact, 80 percent of ASIC design starts are of a density that can be prototyped with a single high density FPGA. FPGAs built on 90-nm process technologies offer core performance in the hundreds of MHz range, I/O performance capabilities in the gigahertz range, gate densities in the millions of gates and costs ranging from under $10 per unit to nearly $1,000 per unit. 

Using FPGAs for ASIC or ASSP prototyping and then migrating to structured ASICs for production can help reduce these development costs and mitigate design risks. Designers can use an FPGA to minimize upfront investment since FPGAs have zero NRE, perform in-system verification to fix design bugs, remove technical risk and demonstrate their technology to customers prior to device production. Designers can also get a head start on system development and qualification with customers in the field, thereby removing market risk while ensuring customer acceptance of the product. As demand for the end product increases, designers can then move seamlessly to a structured ASIC for a fast path to production (turnaround time in weeks) with upfront NRE costs that are a fraction of ASIC NREs. This development flow bypasses the pain and expense of traditional ASIC development while still meeting cost, performance and power requirements.

Case Study

New ASSP ventures face barriers to market entry including tighter venture funding, fragmented end markets and shrinking market windows. One such example is the communication group at Infineon Technologies. A smaller group within a large, multinational semiconductor manufacturing company, the Infineon communication group was designing the MetroMapper 622 ASSP chip, which is a mapper/framer capable of mapping datacom traffic into SONET/SDH transport payloads.

The Infineon group faced multiple challenges such as time to market pressures, limited engineering resources, limited funding for chip development and a set of customers each looking for customization of the ASSP device to better fit their end systems.

Unwilling or unable to risk losing millions of dollars over failed design starts using a standard cell ASIC, the Infineon group sought alternative solutions and elected to design with Altera Stratix FPGAs and HardCopy structured ASICs. The group was able to test the functionality of its design in the field within customer end systems prior to production. Prototyping with the Stratix FPGA enabled minor design modifications and debugging. After in-system validation, the Infineon design was migrated to the HardCopy structured ASIC by Altera’s design center. 

The successful design migration was made possible by footprint compatible packages, equivalent logic element structures, clock networks, I/O buffers, PLLs, memory blocks and similar process technology in the Stratix FPGA and HardCopy structured ASIC. This unique design methodology ensured first-time design success with the HardCopy structured ASIC. It also minimized the upfront costs due to the zero NRE of the Stratix FPGAs and dramatically lower NRE for the HardCopy device compared to standard cell ASICs. Moreover, the flexibility of the FPGA allowed the Infineon group to uniquely customize the designs for its end customers while still getting its product to market early. The 10-week turnaround time for the HardCopy prototypes enabled the Infineon group to quickly ramp its products into production at device costs at a fraction of what the group paid for the FPGA. 

One Infineon customer was concerned about protecting its IP from other users of the ASSP device and requested a custom structured ASIC. The Infineon group migrated the customer’s design to a distinct HardCopy device, thereby limiting its purchase and use to this customer. Infineon was able to capture market share based on meeting the customer’s need for customization using this unique, flexible and cost-effective FPGA to structured ASIC migration solution.

Advantages of FPGA Prototyping

This case study is just one example of the benefits of prototyping with an FPGA and then migrating the design to a structured ASIC. Whether a product is new or mature, these challenges also exist in other markets. It is important that design teams recognize these hurdles and choose a fiscally-sound design strategy that provides the flexibility to make changes as the market dictates. 

FPGAs continue to evolve, narrowing the performance, density and cost gaps with ASICs and ASSPs. In addition, FPGA design flows are increasingly mimicking ASIC/ASSP design flows. These methodologies differ, however, in that proprietary FPGA design software offers some innovative technologies to speed system design and take advantage of the programmable nature of FPGAs for in-system verification. 

Prototyping an ASIC or ASSP design using FPGAs can relieve the time bottleneck and remove the high-caliber compute resources required to functionally verify a sub-average to large-sized design. In addition, prototyping can provide other, more enticing, benefits. A single prototype, for example, can serve to verify hardware, firmware and application software design functionality before first silicon is brought in-house.
    
In the ASIC/ASSP development process, hardware developers are concerned about how they will integrate external IP they don’t fully understand. The IP can be hard or soft, with each type presenting different integration challenges. The need to develop derivatives must be accounted for in the original design—if not, developing a derivative can become as tough as developing a new product. 
    
Software developers need to use real hardware during design work because simulation models can’t provide the speed they need—even when accelerated. Software developers want to use their familiar development and debug environments, not Verilog and a waveform viewer, to debug their code. 
    
A FPGA-based prototype can address the needs of both hardware and software developers. Given low design stability, firmware and application software, developers usually request hardware design changes that require a re-configurable prototype. To enable that, the FPGA on the prototype must be re-programmable. SRAM-based FPGAs provide this capability. In addition, since the speed of the system must be high enough to enable fast OS booting and application software testing, high-performance FPGAs can do the trick with block speeds of more than 350 MHz and average system speeds of approximately 200 MHz. 
    
To prevent intellectual property theft, the design has to be “secure” as FPGA-based prototypes are moved around from one geographic location to another. A high-density FPGA can incorporate a design security feature based on a 128-bit advanced encryption standard (AES) algorithm. The key is stored in a non-volatile location in the device itself, which remains reprogrammable with the key.
    
With large device pin-out counts and small pin spacings, successfully assigning physical pin numbers to ports of each FPGA design can be influenced by several factors, including routability of the FPGA, placement of the FPGA relative to its neighboring components on the PCB, system interface location constraints and PCB routability. Tools that provide pin assignment flexibility, available in proprietary FPGA design software, are critical to the pin planning process.

ASIC and ASSP hardware designers have an affinity for scripting. Their flows use and apply automation within a single tool flow and between multiple tools used in projects. Initially, as a design is compiled into a FPGA, designers may use graphical tools. However, as design iterations increase, the need to automate becomes paramount.
Proprietary FPGA design software provides tool command language (Tcl) scripts, allowing the designer to perform a wide range of functions, such as compiling a design or writing procedures to automate common tasks. 
Medium to large scale designs will often require more than one person to design and implement the design blocks. Various teams working in different locations is the norm, especially with high-end ASIC design work. Either an entire FPGA or a portion of an FPGA should be dedicated to each team, providing a block-based design flow that enables design, optimization and locking down the design one block at a time.

Proprietary FPGA design methodology enables teams to independently create and implement each logic block into a hierarchical or team-based design. Constraints can be used either with custom blocks of logic or with pre-verified IP. The FPGA design flow guarantees repeatable placement when implementing a module of logic in a current project or exporting the module to another project. This methodology enables performance preservation of each block during system integration. Additionally, logic-locked blocks can be reused in other designs, further leveraging resources and shortening design cycles.

Occasionally hardware and firmware engineers must debug incorrect memory states or force incorrect memory conditions to test error handling. Engineers require the ability to read, write, dump and initialize memory in their designs. Proprietary FPGA design software provides read and write access to in-system FPGA memories and constants through the Joint Test Action Group (JTAG) interface, making it easier to test changes to memory contents in the FPGA while the device is functioning in the end system. The ability to read data from memories and constants allows the hardware engineer to quickly identify the source of problems.

Verifying a design using state-of-the-art 90-nm FPGAs for prototyping reduces risk. The risk can be further reduced by migrating the FPGA-verified design into structured ASICs. Structured ASICs can shrink time-to-market further as the additional design effort required for migration is minimal compared to re-targeting the design to an ASIC or ASSP technology. A structured ASIC is a non-reprogrammable device seamlessly migrated from a design that is prototyped in a FPGA. Based on a fine-grained architecture of transistor cells, proprietary structured ASICs customarily are fabricated on the same advanced 90-nm process as the FPGA.

Conclusion 

Whether introducing a new product or updating a current version of a design, certain market entry barriers, including time to market pressures, limited human and financial resources and increased design complexity can derail success of a product even before the first device is sold. In order to overcome these hurdles, IC manufacturers must choose a cost-effective design strategy that is flexibile enough to allow changes within this unstable market environment. 

ASIC and ASSP prototyping using state-of-the-art 90-nm FPGAs, then migrating to structured ASICs for production, has several time-to-market and cost-saving benefits, including design automation, flexibility and reduced development risk. ASSP manufacturers such as Infineon Technologies have taken advantage of these benefits to accelerate product entry into dynamic markets where standards are always changing. 

Infineon also favors the design flexibility afforded by a FPGA prototype-to-structured ASIC migration solution because it enables the company to easily create customized designs according to individual customer specifications, including those concerning IP protection. 

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Posted by on in IC Design

b2ap3_thumbnail_500px-SYNOUT.pngSynopsys Inc. is offering the IC Compiler 2010.03, a physical implementation solution delivering up to 2.5x faster performance on multicorner/multimode (MCMM) designs, and enhanced in-design technology for faster design closure.

IC Compiler's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has production support for all known 28/32nm design rules for major foundries, with several customer tapeouts underway.

IC Compiler 2010.03 offers performance improvements across the board. It provides 2x faster time to initial floorplan creation and on-demand loading, which offers 2x to 3x faster time to final floorplan creation. IC Compiler 2010.03 also includes 2x faster pre-route feasibility engines and generates interactive reports that help significantly reduce iterative cycles during early stages of design. Faster MCMM scenario processing, core engine improvements and multimode clock tree synthesis deliver faster timing convergence.

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b2ap3_thumbnail_download.jpgCONTRIBUTION BY STUART EMMETT – FREELANCE INDEPENDENT TRAINER AND CONSULTANT WHO TRADES UNDER THE NAME OF LEARN AND CHANGE

First of all, let’s look at a summary of what a systems thinking view tells us about the supply chain. Some of this will be well known, so others parts maybe new. However, the main message is to note and be aware of the multiple inter connections and inter dependencies.

  1. The supply chain is a process that has a purpose.
  2. The process is either, the transformations (inputs-process-outputs) into products /services;  and/or,  the positive and negative feedback from the  output transactions that may change the inputs, outputs and/ or processes
  3. All of the supply chain processes have dependency, variability and interfaces (e.g. an interplay of relationships) as
  4. Supply chains will change in response to feedback (as shown in the well known Forrester effect on inventory amplification, for example, as shown in the “Beer Game”)
  5. Besides feedback, supply chains also function with the interactions in and between its parts. Tinkering only with the parts will sub optimise the whole, as the whole is formed by the sum of the parts. Additionally when focussing only on the parts, the whole is not being fully considered, (consequently, the purpose and meaning for the whole is now lost and is possibly, unachievable; effectively, the original purpose has been changed).
  6. The parts have to be arranged in specific known ways to make the required wholes that will achieve a specific purpose; therefore we must fully understand the connections and interactions of the parts when we look at the required wholes.
  7. This will involve a consideration of not only our own whole system, but also the wholes of the others and the connections to purpose, processes, structures, as well as the power and the people aspects.

The above link usefully into my earlier Supply Chain Rules 1-3 (from Emmett 2005; “The Supply Chain in 90 minutes”)

SUPPLY CHAIN RULE NUMBER 1: “WIN THE HOME GAMES FIRST”

Many companies start into Supply Chain Management, by working “only,” with the closest suppliers and customers. They should however, first ensure, that all of their internal operations and activities are “integrated, co-ordinated and controlled.”

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Korean semiconductor company MagnaChip has a chequered history stretching back three decades.

Originally the system ic division of Hynix, which was created when LG Semiconductor and Hyundai Semiconductor merged, MagnaChip was spun off as a standalone company in 2004. While Hynix retained the memory side of the business, MagnaChip focused on analogue and mixed signal technology. 

Business issues saw MagnaChip confront a number of problems. Plans to float the company on the New York Stock Exchange faltered and a downturn in its fortunes saw it filing for Chapter 11 bankruptcy protection in the US. Following a couple of changes of ownership, the company appears to be back on its feet; the planned IPO took place in 2011 and MagnaChip is now valued at around $600million. 

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Posted by on in Software Developer

b2ap3_thumbnail_software-developer-vs-software-engineer.jpg

Building software is hard: successfully bringing a new software product from conception to market is harder. Building a successful software company that develops and markets multiple software products is harder still.

The days of ‘build it and they will come’ are over. Simply creating a great piece of software and waiting for the customers to knock on your door no longer works – if it ever did.

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b2ap3_thumbnail_img12-4.gifAnecdotal mentions of hefty sums of more than $25m just to buy one mask set and total design costs reaching into many hundred million dollars, seem to mark out ASIC design as a rich person’s game. But these figures are only for the leading-edge processes typically used for high volume consumer products like smartphones.

For internet of things (IoT) applications, where integration levels are lower and the need to interface with the real world mandates the use of analogue circuitry, mature “more than Moore” process technologies are more suitable. Here the costs and risks of using ASIC technology are very different.

ASIC design and production has actually become cheaper for many projects, to the point that many people who used to believe field-programmable gate arrays or microcontrollers coupled with discrete analogue devices were their only options are finding out that the dedicated ASIC approach is more cost-effective.

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b2ap3_thumbnail_download-2_20160720-053121_1.pngFollowing Apple into the IC design market, Google Inc is buying a chip design team company Agnilux Inc., according to reports. The chip design firm was established by former design engineers who had been brought into Apple and then quit to form their own company.

Agnilux was founded in about December 2008 but very little is known about the company except that the name is compound of the Sanskrit word for fire—agni—and the Latin word for light—lux.

It was speculated that the design team could be proposing to reduce server power consumption by designing a multiprocessing ARM chip as a server engine, just as the team when working at Apple is believed to have worked with an ARM architectural license to improve power efficiency and extend battery life.

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b2ap3_thumbnail_download-1_20160720-052929_1.pngWhenever I work on any supply chain process improvement engagement, I intuitively classify them as either “Routine Problem” or a “Non- Routine Problem”. A routine problem is something which has a straightforward simple solution. Other simple way to look at routine problem is where you can apply an algorithm to solve the problem – If your supply side costs are high – A cost based optimization engine used effectively will help. However “Non-Routine Problems” are more abstract, problems where even supply chain veterans do not have a simple explanation. (Another rather easier way of identifying a non-routine problem is when your boss explains you the problem and then – There is a long silence from both sides).

With the increasing complexity owing to global nature of today’s supply chains, more and more supply chain problems are falling in the latter category. Couple this with increasing number of events which can cause volatility in your demand and supply markets. Solving a “Non-Routine” problem requires a strategy unique to the problem. One of the common strategy is to think of the problem in terms of “Waste”. A supply chain is not efficient may be because potentially there is a lot of waste that has been created due to various imbalances, events, customer demands, supply fluctuations etc. That is where data analytics can play a huge role in not only quickly identifying this waste but also anticipating the future waste.

These days I am working on a “Non- Routine” problem – “Improve the production capacity utilization so as to cover up the fixed plant costs and sell the additional delta production (due to improved utilization) for a discount (so as not to increase inventory costs)- And generate extra revenue in the entire process”. I classify this as a non-routine problem because a single algorithm will not be able to solve this problem. Capacity decisions impact all areas of operations management as well as other functional areas of the organization. Also it is important to understand that the focus is on improving utilization (=Actual Output/Design Capacity) and not on improving efficiency – (=Actual Output/Effective Capacity)

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b2ap3_thumbnail_download_20160720-052735_1.pngThis paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place of IP modules yet to be designed. The goal of the first model use-case is to reduce the likelihood of human error resulting in IC functional faults. The goal of the second use-case is to develop an executable specification upon which the detailed design of IP blocks may be based.

1. Introduction:

As the size and complexity of SOCs and ICs increases, the critical task of finding and eliminating human error becomes more and more difficult – even for digital-only chips. Adding analog circuitry magnifies the problem. By its very nature, analog design and verification is more complicated than digital. When the design of analog modules is outsourced, the experience can be frustrating and traumatic enough for the faint-of-heart to avoid future purchases of analog IP altogether.

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b2ap3_thumbnail_programmer.gifWhen I published "The Zen Programmer" book in 2013 [6], a manager from a big company sent me an email. In this book I describe how I applied Zen to my daily work and how I am able to keep balance despite how hard I work.

The manager told me that almost everything I wrote was just plain wrong. For example, I believe that there is nothing like a career one can have; he responded that my career would be successful if I just would do what my manager commanded. "Jump if your boss tells you to jump", he wrote.

This certainly is not how I want to live. A career is an illusion, a theoretical term, but Life is not. "Making a career" is sometimes just the wrong thing to run after, and that can cause serious harm to you.

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Handheld PCs, PDAs and smart cell phones are showing up in new applications every day. These new products are made possible by the adoption of wireless technology and the internet. Taxi and delivery services, vendors at fairs and swap meets and many other mobile merchants are now able to accept credit cards in the field.

Semtek Corp, a San Diego based company that manufactures credit card readers, was developing a new product. “Our new reader had to be small, very low power and low cost,” remarked Dennis Mos, VP Sales and Marketing at Semtek.

Size, power and cost are all benefits of ASIC technology; however, developing an ASIC, particularly a Mixed Signal ASIC, can be expensive and time consuming. Such an undertaking may prove especially risky for new product like Semtek’s wireless credit card reader. Many engineering managers are of the mind that ASIC’s are best left to the “Big Boys.” And considering the high cost of tools, masks and fabrication they are probably correct, but not completely.

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Posted by on in IC Design

b2ap3_thumbnail_1115_TI_Glaser_F1.gifSTMicroelectronics has extended its range of high-side current-sensing portfolio with the TSC102 that simplifies design of smarter and safer systems by sensing current more accurately and giving designers extra flexibility to adjust the sensor's output before inputting to the system controller. The amplifiers provide a fully configurable integrated signal-conditioning amplifier that target automotive, industrial and computer applications.

Accurate sensing of system current is central to effective control of precision equipment performing functions such as positioning, variable-speed operation, or continuous self optimization to maximize energy efficiency. Precision current sensing is also important in a wide variety of safety mechanisms, such as auto-stop for vehicle-window lifters to prevent discomfort or injury to users.

ST's TSC102 is designed for direct connection to a small current-sensing resistor sitting at a voltage up to 30V. This direct connection allows a system to be monitored without disturbing its ground connection, which is essential in applications like automotive systems or for monitoring power supplies with multiple outputs. The device also has rugged inputs to survive applied voltages ranging from -16V to 60V. These voltages can arise in systems where many loads are switching continuously or there is a risk of a reverse battery connection, such as in vehicle electrical infrastructures.

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b2ap3_thumbnail_logistics_arrows_earth_PA_md_wm.gifEstablishing an environment of end-to-end supply chain visibility leads to more efficient manufacturing, lower costs and fewer incidents of a mismatch between supply and demand. In implementing that visibility, companies look at everything from sourcing raw materials, to manufacturing, to supplying the sales channel with finished product. However, a frequently missing component in a supply chain visibility strategy is transportation management, or the not-so-simple act of getting finished goods and raw materials from one location to the next.

With increasingly tight margins and higher freight costs, even small supply chain oversights can cause unnecessary expense, in terms of scenarios like product write-offs or write-downs that may occur as a result of an oversupplied sales channel, missed sales opportunities due to an undersupplied sales channel, or higher-than-necessary costs due to a failure to monitor raw materials prices across multiple sources. But beyond that, the biggest "hidden" cost of a poor supply chain is transportation — and the cost of getting goods from one place to another may well mean the difference between profit and loss. Management of freight costs, especially in a large enterprise, becomes extremely important, and the connection between visibility of freight as a component of the supply chain, and the transportation economies that can come as a result, quickly becomes apparent — and in a low margin business, transportation economies are a vital component of establishing profitability.

Visibility isn't just a buzzword

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Abstract:

The development of analog IP blocks shows its own difficulties in that it is still unclear, today, what characteristics those blocks must actually have and how they should be approached. Particularly, there is no broad, openly available stardard for analog IP.

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Reduce testing time & get feedback faster through automation. Read the Benefits of Parallel Testing, brought to you in partnership with Sauce Labs.

With the vast array of technology, language and platform choices available today, it can be very difficult to figure out where to best invest time in training your skills as a software developer.

I’m often asked advice on how to be a better programmer.

Most often the question someone asks is based on whether or not they should invest their time in a particular programming language or technology versus another.

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b2ap3_thumbnail_download-2.pngThese days, a typical corner (TT) is no longer typical for most applications. For that matter, standard PVT Corners (FF/TT/SS), generally, do not represent the exact environmental conditions in which an ASIC/SoC will be functioning. This means the voltage may not be a nominal Vdd in a typical case or Vdd±10% in an extreme case; and the temperature may not be 25C in a typical case or 125C/-40C in extreme cases. Also, in today's market, everyµW of power saved, and nS of delay avoided, makes a significant difference in a product's performance and cost. Therefore, it is important to know how a system behaves under real-time PVT conditions. One needs to characterise foundation IPs at these special (custom) corners to avoid overdesign and achieve optimal product for best power and performance. When estimating the power and timing numbers of an IP at a custom corner (e.g., @95C and Vdd+3%), it is not easy to derive values from regular SS, TT, and FF characteristics as these may not support linear extrapolations. Even small errors in calculation can be very risky. One approach is to use characterisation tools (e.g., Silicon Smart from Synopsys) that can easily characterise foundation IPs to estimate power and performance of an SoC at any custom corner with substantial accuracy using reference ".lib" files.

Ensuring accuracy

In order to generate an accurate custom corner ".lib" file, one must ensure that a reference ".lib" file, which is already provided by an IP vendor, can be generated using the setup. The better co-relation achieved ensures more accurate ".lib" generation for the custom corner. Various options and settings available in the tool enable proper alignment of setup to adhere to the processes followed by different vendors to generate highly accurate ".lib" files. The tool also provides the flexibility to choose between different simulator environments available in the market (e.g., HSpice, Spectre).

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b2ap3_thumbnail_9TpdK4aTE.gifChip design costs are expected to shoot up, but software—not hardware—is playing a much greater role in the problematic equation.

This is according to Mentor Graphics Corp. chairman and CEO Walden Rhines, who said that the shift in the equation will require a new type of EDA technology—embedded software automation (ESA)—as a means to attack the problem.

Rhines warned that IC design costs for many devices are projected to hit the dreaded $100 million level within the next three years. Not long ago (and even today), IC design costs ranged between $20-to-$50 million.

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b2ap3_thumbnail_download-1.pngWhat if the supply chain community could emulate the “Internet world” and create a universal, open logistics network that is economically, environmentally, and socially efficient and sustainable? Such a concept exists, and it’s called the Physical Internet. Today the Physical Internet is a vision for an end-to-end global logistic network, but there are plans to turn it into a reality by 2050.

Companies constantly strive to improve the efficiency of the logistics networks that move their goods worldwide. Although performance levels have increased significantly over recent decades, they are far from satisfactory. For example, too many containers and freight vehicles transport empty space or are idle because of operational delays. All too often, disruptions prevent products from reaching consumer markets, adding to the waste that pervades many logistics networks.

The Physical Internet proposes to eliminate these inefficiencies in much the same way that the Internet transformed the flow of information around the globe.

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b2ap3_thumbnail_images-1.pngApplication specific integrated circuits (ASICs) typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems. Unlike multi-function standard product ICs such as a micro-controller that can find its way into a wide variety of applications, ASICs are designed for one specific application and generally for one specific product or product family.To better understand the role and applicability of ASICs, it is important to briefly review their historical origins.

The first integrated circuits from the early ‘60s contained just a few transistors and performed simple digital logic functions such as "and", "or", "nor", etc. These were called SSI devices, meaning small-scale integration. As photolithography techniques improved, more and more transistors could be built on a single sliver of silicon. Soon, chip companies were developing medium scale integration (MSI) functions like flip-flops, buffers, latches, etc (10-100 transistors). Large-scale integration or LSI (100-1,000 transistors) and eventually VLSI (up to 100,000 transistors) ICs followed, providing lower system costs and higher levels of performance. Today, of course, we have digital chips in excess of a billion transistors thanks to advanced sub-micron lithography and the low voltage, high speed processes upon which they are built.

The first digital ASICs were built using a standard cell library consisting of fixed-height, variable-width ‘tiles’ containing the digital logic functions discussed above. The ability to reuse these blocks over and over saved time and money when designing a custom logic IC. Analog ICs were initially comprised of a pair of matched transistors and soon expanded to include rudimentary op amps, voltage regulators, comparators, timers and much more.

Demands of analog
Analog applications typically involve much higher voltages, so these ICs needed their own unique set of manufacturing processes. More recently, market demands for smaller size, higher speeds and lower power consumption have forced a merging of analog and digital functionality on a single silicon chip. Cells consisting of the basic analog building blocks discussed above were created and added to the digital libraries. These Analog cells were restricted to the digital fab processes developed for predominately logic applications.

Today, most ASIC companies offer some degree of analog functionality as a part of their services. In many cases, the analog functions are mimicked with digital design techniques. In others, compromises to the analog functionality must be made to facilitate the use of standard library cells that are designed to yield well in the fab processes developed for high speed, high density, low power digital designs. Often, these chips are referred to as Mixed-signal ASICs or as big “D”, little “A” ASICs, meaning high digital content and minimal analog content.

Analog ASICs play a critical role in our lives. Without them, none of the portable electronic devices we use in our daily lives would exist. Imagine a world without cell phones, MP3 players and navigation systems. Building them with standard products would make them prohibitively expensive and physically impossible to carry in our purses or pockets. Every automobile contains dozens of ASIC chips for everything from climate control to airbag deployment; suspension control to entertainment systems. ASICs also play important roles in applications for hospital medical equipment, eMeters, home appliances such as washers and dryers, scuba gear, hearing aids, and much more.

Picking an ASIC design partner
The analog ASIC market is huge. In fact, research firm IC Insights reports that almost 60% of the nearly $37B of analog ICs sold in 2010 were ASICs. Yet very few mixed-signal ASIC design houses fully understand the implications of custom analog design and its applicability to analog-centric ASICs. ASICs requiring high analog content should be directed to those design houses that specialize in analog circuit design rather than those who simply select analog IP blocks from a library. Analog ASIC companies have large staffs of competent, experienced, analog engineers with expertise in a wide range of analog functions.

Reviewing an ASIC house’s patent portfolio as a quick guide as to the creativity of its engineering team will serve as a first order measure of its analog expertise.

Clearly, the large analog IC houses (like ADI, Linear Tech, Maxim, National, TI) have patent portfolios a mile deep. Those that also engage in analog ASIC development set high bars regarding who can access this capability and impose high minimum order requirements. For example, TI reports that their application-specific analog business focuses on a small number of large customers like Seagate, Sony, Samsung, Hitachi Global Storage Technology, Toshiba and a few others that require custom application-specific products. Minimum annual unit and or dollar volumes force the majority of the smaller customers to seek out independent analog or mixed-signal ASIC design houses.

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b2ap3_thumbnail_images.pngFollowing a series of fatal accidents in the mid-1990s, a formal investigation was conducted with the Therac-25 radiotherapy machine. Led by Nancy Leveson of the University of Washington, the investigation resulted in a set of recommendations on how to create safety-critical software solutions in an objective manner. Since then, industries as disparate as aerospace, automotive and industrial control have encapsulated the practices and processes for creating safety- and/or security-critical systems in an objective manner into industry standards.

Although subtly different in wording and emphasis, the standards across industries follow a similar approach to ensuring the development of safe and/or secure systems. This common approach includes ten phases:

1. Perform a system safety or security assessment
2. Determine a target system failure rate
3. Use the system target failure rate to determine the appropriate level of development rigor
4. Use a formal requirements capture process
5. Create software that adheres to an appropriate coding standard
6. Trace all code back to their source requirements
7. Develop all software and system test cases based on requirements
8. Trace test cases to requirements
9. Use coverage analysis to assess test completeness against both requirements and code
10. For certification, collect and collate the process artifacts required to demonstrate that an appropriate level of rigor has been maintained.

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