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b2ap3_thumbnail_AMS_Martin_pic_blog2.jpg1 Abstract

This article provides an insight into various approaches followed for Analog and Mixed Signal (AMS) modeling and the associated challenges. The emphasis is on analyzing various approaches and finally providing options that can be used right from architectural exploration to implementation with a co-simulation based approach.

2 Introduction

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b2ap3_thumbnail_1024px-Wipro_Logo.svg.pngLUSTENAU, Austria & OLNEY, England—(BUSINESS WIRE)—November 4, 2008— Wipro NewLogic and IN2FAB Technology today announced the launch of a new facility to provide design porting services for analog mixed signal and custom IC designs between foundry processes and geometries. The co-operation enables IC designs and IP to be ported to a manufacturing standard in just a few weeks, typically offering up to 10X reductions in cycle time and engineering costs as well as freeing up customers engineers to focus on other potentially higher value added activities.

Known as Port-on-Demand, this service line will reside within Wipro NewLogics Product Engineering Services division based in Bangalore, India and Lustenau, Austria.

Wipro NewLogic has assembled world class semiconductor design and engineering operations in India and Europe offering a full capability for IC design services with competitive cost and time to market benefits. Over several years IN2FAB has established a strong track record of porting silicon successfully with its migration tools and methodologies covering all CMOS geometries including most recently the 45nm node. IN2FAB will provide its migration tools, methodologies and infrastructure to the Port-on-Demand facility.

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Predictions that Moore's Law cannot continue beyond the next process node have been proven false for a decade now at least for the digital world.

Yet while many roadmaps continue to show a path to 10nm and beyond, there is real evidence that, since the 28nm node, the industry is failing to keep up with the progress anticipated by Moore's Law. And analogue and mixed signal (AMS) designers are facing particular difficulties. 

In his keynote to last month's IPSoC 2012 conference in Grenoble, Joachim Kunkel, general manager of the Synopsys Solutions Group, highlighted some of the challenges facing analogue and mixed signal IP designers at 20nm. "We have been tracking the adoption of new technology nodes and while it has been fairly consistent up to the 32/28nm node, there is now a noticeable slow down. We have seen a significant change of procedures as customers start looking at 20nm," he said (see fig 1). 

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Korean semiconductor company MagnaChip has a chequered history stretching back three decades.

Originally the system ic division of Hynix, which was created when LG Semiconductor and Hyundai Semiconductor merged, MagnaChip was spun off as a standalone company in 2004. While Hynix retained the memory side of the business, MagnaChip focused on analogue and mixed signal technology. 

Business issues saw MagnaChip confront a number of problems. Plans to float the company on the New York Stock Exchange faltered and a downturn in its fortunes saw it filing for Chapter 11 bankruptcy protection in the US. Following a couple of changes of ownership, the company appears to be back on its feet; the planned IPO took place in 2011 and MagnaChip is now valued at around $600million. 

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b2ap3_thumbnail_download_20160720-052735_1.pngThis paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place of IP modules yet to be designed. The goal of the first model use-case is to reduce the likelihood of human error resulting in IC functional faults. The goal of the second use-case is to develop an executable specification upon which the detailed design of IP blocks may be based.

1. Introduction:

As the size and complexity of SOCs and ICs increases, the critical task of finding and eliminating human error becomes more and more difficult – even for digital-only chips. Adding analog circuitry magnifies the problem. By its very nature, analog design and verification is more complicated than digital. When the design of analog modules is outsourced, the experience can be frustrating and traumatic enough for the faint-of-heart to avoid future purchases of analog IP altogether.

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