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Power Analysis Throughout the Physical Design Flow
In most cases today, IC power analysis efforts are mainly focused at signoff. Even though some place and route (P&R) solutions provide simple checks at the floor planning stage, there are a lot of opportunities to improve power analysis capabilities during design, and to align and integrate these with the signoff tools and the overall design flow.
Although every semiconductor company handles power analysis slightly differently, Figure 1 shows an idealized approach in which power analysis is embedded across the entire IC physical design flow. IC designers get their specifications from a cross-functional architecture power constraints definition, which is often called the “power budget.” This budget, which typically is fixed before any new IC implementation is started, specifies the maximum power permitted for the system, the board and the IC packages. At this point, the budget is essentially a rough estimate based on the know-how and experience of the IC, package and board engineers involved in the requirements definition for each new product development project. Once a high level budget is defined, it can be used to project the expected current flow and a power grid (PG) definition can be derived and partitioned into more detailed domains within the IC. The power grid should be able to accommodate the maximum expected current flows without a significant voltage drop given a design margin of around 10%. This sets the constraints for IC physical design implementation in a conventional P&R flow, which ends in a final power signoff analysis that validates the design against the power budget. Unfortunately, the process does not always proceed in this idealized, linear fashion. When the budget estimates are off, or the implementation is more difficult and power hungry than anticipated, “making ends meet” can become painful and lengthy. This article describes in more detail how power constraints are enforced in the design flow and highlights areas of opportunity to improve the results, eliminating surprises, with a more robust power analysis capability.
Signoff Power Analysis
Initially, in the early 2000s power analysis tools were used as a final signoff check to insure that the IC design did not have a major voltage drop or current density issue. At that time there was a relatively low probability that a design would fail the check and cause a big schedule slip, so it was typical to run the checks only at final signoff. However, as we have advanced to more complex nodes, and more complex power architectures, designers’ need for more comprehensive and accurate power analysis has grown. Nowadays, power analysis includes static and dynamic IR drop, current density (CD) checks to eliminate problems associated with EM-induced failures, ESD checks and in-rush effects (i.e., the effect of one power domain switching on or off on the rest of the chip).
However, detailed power analysis is still often left until signoff for one main reason: power analysis tools are not well integrated into the physical design flow. If power issues are first discovered at signoff, the designers may be able to resolve the issue with a simple tweak of a power network here and there, or by adding a decoupling capacitor or a pad at the right spot, if there is room. But sometimes power problems require a redesign of the power grid or change in the floor plan. This could have a drastic effect on the time to tapeout.
To avoid having major power issues at the signoff stage, designers typically over-design the power grid to make sure it will be robust enough to avoid voltage drop and current density problems. Because the power grid can use up to 30% of the routable area of a given die, over-designing the power grid negatively impacts the routability of the design, which at 28nm and below can have a tremendous impact on maximum performance and time to market. Congestion forces designers to either selectively reduce the size of the power grid in crowded areas, or reduce routing congestion by lowering the gate utilization rate, which consumes more layout area. If modifying the power grid design results in power issues at the signoff stage, designers will have to revisit the layout with ECOs that lengthen the critical path to tapeout. Semiconductor companies working at 28nm and below are spending more and more resources on preventing power issues in their designs, and these companies are pressing EDA providers to extend their solutions beyond signoff-only power analysis, and to add more sophisticated checking and “what-if” capabilities earlier in the design flow.
Upstream Power Analysis
An “upstream” power analysis solution would be able to guide the place and route (P&R) floor planner at the early stages of physical implementation. Some existing P&R solutions provide rudimentary power feedback at this stage, but these are usually not consistent with the signoff checks that will be applied at tapeout, so there is still a high risk of late stage problems that could have a major impact on the design due to lack of correlation with the signoff tool.
An improvement in the flow would consist of an upstream power analysis application that can be leveraged for early macro-placement and floor planning power analysis. When the preliminary floor plan is completed and all the macros and standard cells “seeds” are placed and legalized, the P&R tool typically creates a power grid mesh to meet power density constraints, but it is not finalized at this stage. There will still be a number of short, open, and unconnected instances, as well as missing power vias resulting in floating power rails and poor pad connections. At this point in the process, designers need a power analysis tool that is extremely fast—an order of magnitude faster than signoff—allowing rapid analysis and little impact on the IC design implementation time. The analysis should be based on the actual signoff rules and include static power analysis and power grid integrity checks with an accuracy of about 20% (compared to signoff accuracy).
Ideally, this solution would provide designers with design recommendations, like the number of pads and current sources needed, power grid width and pitch hints. It should also include a “what if” capability allowing designers to explore the impact of adding or removing pads, widening straps and other alternatives. It would enable IC architecture exploration driven by power analysis where the P&R tool could generate several variant floor plans and the power analysis solution could assess and rate each version, enabling the designer to choose the floor plan with the best power robustness. Similarly, the P&R tool could generate several alternative power grids for a given placement, which would allow the designers to pick and choose the most robust power grid implementation. An even more advanced capability would provide early voltage drop evaluation using dynamic power analysis, again based on signoff criteria. For instance, designers should be able to monitor the worst voltage drop during the entire simulation window at each instance or the worst voltage drop during a defined switching window.
An integrated upstream power solution would enable designers to implement an efficient floor plan and power grid without over-designing and giving up precious real estate. At the same time they would have confidence that all signoff power constraints have been met and there will be no surprise violations at signoff time.
Post-CTS Power Analysis
Another opportunity for power analysis within the physical implementation flow is a post-CTS (post clock tree synthesis) power check. An integrated, signoff-based power analysis solution would allow designers to optimize their post-CTS design and help ensure readiness for signoff verification.
At this stage, the floor plan is frozen, all the macros and standard cells placements are legal, 75% of the power grid mesh is in place, and the clock tree is in place. There are typically still a few shorts, opens, or unconnected instances and some missing power vias and floating power rails. To resolve these issues, designers need to run both static and dynamic power analysis with an accuracy of 10% compared to signoff quality, assuming all design parameters are constant (i.e., the only anticipated changes are optimizations on selected data paths and signal nets, and perhaps some post-route optimization). A post-CTS power analysis solution should perform power grid integrity checks, in addition to the typical voltage drop and current density checks. There should be specific checks for clock tree power issues, for example, finding large clock buffers belonging to the same clock within the same rail segment. In this case the power grid might have to be “beefed up” to support high current, typically by adding additional straps where the density of these clock buffers is high.
At this stage it would be very beneficial to provide designers with a clock power map that highlights specific regions of the clock tree, in addition to the conventional power density map. The performance of a post-CTS power analysis tool that provides these capabilities should be marginally faster (say 2X) than the full signoff tool to ensure minimal impact on design time. An incremental “what if” analysis capability at this stage would allow additional optimization, such as moving selected clock cells to check the impact on the voltage drop.
Additional Power Analysis Opportunities
A comprehensive power analysis solution should be able to cover upstream, post-CTS and signoff design checks in a consistent manner, as described earlier. There is also a need for power analysis tools that can help guide the definition of power grid constraints as show in Figure 2.
Figure 2. Power Grid Topology Recommendations Flow
The concept is to create a power grid cell sample (say 30 x 30 tracks for instance) including probing points. The sample would have average current source representation and multi-scenario current source placements (best, worst, average). The tool would then extrapolate the grid by replicating the power grid cell and then run a full power grid simulation to detect violations, generate “what if” scenarios, and provide power grid recommendations based on the analysis of these scenarios. Designers would use this capability in an interactive mode, allowing them to explore many alternatives while the tool performs the tedious computational activity.
Power analysis is mandatory for signoff verification, and because there is little help for designers early in the design process today, designers often over-design to make sure they do not have catastrophic power issues late in the design cycle that they cannot easily solve. Unfortunately, over-designing the power grid has a negative effect on performance. A comprehensive power solution should provide critical information during upstream (floor planning) and post-CTS stages to allow designers to explore different architectural tradeoffs, to increase the robustness of their designs, to keep their power margins tight, and to avoid any late surprise at signoff. To be effective, such a solution must utilize the actual criteria and power checks required to pass signoff, albeit at different accuracy levels and turnaround times as appropriate to each stage of the design process.