b2ap3_thumbnail_AMS_Martin_pic_blog2.jpg1 Abstract

This article provides an insight into various approaches followed for Analog and Mixed Signal (AMS) modeling and the associated challenges. The emphasis is on analyzing various approaches and finally providing options that can be used right from architectural exploration to implementation with a co-simulation based approach.

2 Introduction

In today’s world, AMS models are used for architecture exploration and performance evaluation. The AMS models are also used in place of mixed signal IPs for faster simulation in co-simulation environments. The conventional co-simulation approaches are time consuming with respect to setup and execution. The article starts highlighting the challenges involved in AMS designing and modeling, and then different modeling techniques are explained in brief including SystemC AMS with a case study of DPLL model in the end.

3 Challenges in AMS Design and Modeling

4 Analog and Mixed Signal Modeling Approaches

VHDL-AMS, Verilog-AMS and SystemC-AMS allow modeling of discrete and continuous-time signals or a combination of both. All the three afore said HDL languages can represent AMS systems at a higher level of abstraction by bringing down the simulation time while providing the intended functionality of the design. The following sections describe the process of modeling in each of the languages and finally a comparison of all the available modeling options to give a clear understanding of the pros and cons of each language.

4.1.1 VHDL – AMS

VHDL-AMS is an extension of VHDL to model AMS circuits and systems. Both electrical and non-electrical systems can be described at different levels of abstraction using VHDL-AMS. The VHDL – AMS cycle starts with initialization phase, which consists of the following main steps.

Both Verilog-A and SystemC-AMS follow a similar initialization technique. The actual VHDL-AMS simulation cycle begins with the computation of analog solution points (arrow 1 in Figure 1). This continues until the next digital event is scheduled or an event occurs on the analog and digital interface (arrow 2 in Figure 1). To compute a digital evaluation point, signals are updated first. After that, any triggered processes are executed until they settle. If the time for the next digital evaluation Tn is equal to current time Tc, the digital simulator is called again (arrow 3 in Figure 1). If Tn is not equal to Tc, the analog solver is called, and the next cycle begins (arrow 4 in Figure 1). This continues until the end of simulation is reached (arrow 5 in Figure 1).

Figure 1: VHDL-AMS simulation cycle – Execution

4.1.2 Verilog – A

Verilog – A allows the designer to capture the behavior of AMS designs at different levels of abstraction. Figure 2 indicates the typical Verilog – A simulation cycle.

Figure 2: Verilog – AMS Simulation Cycle

4.1.3 MATLAB - Simulink

MATLAB - Simulink or other interpretation tools can be used to model AMS systems if supporting libraries and functions are available. Simulink has an inbuilt analog tool set which can be used for AMS modeling and the accuracy results are comparable to that of spice simulation results. At higher levels of abstraction, this can be used for architectural exploration where the feasibility of a particular architecture and its functionality through simulations can be explored. The high cost of simulators, the increase in simulation time as the level of design abstraction reduces and problems with co-simulation make Simulink a non-preferred flow for AMS designs.

4.1.4 SystemC – AMS

SystemC-AMS is an extension of SystemC that uses an open and layered approach. The base layer is the existing SystemC 2.0 kernel. On top of the base layer, two sets of layers are defined: Interface to the existing SystemC layers, (e.g., discrete event channels), and a new set of AMS layers such as the synchronization layer, the solver layer, and the user layers.

The user view layer provides methods to describe the continuous-time models in terms of procedural behavior, equations, transfer functions, state-space formulations, and as netlists of primitives. Due to its open source architecture, the user can add additional features to the simulator depending on their application. SystemC-AMS uses a Synchronous Data Flow (SDF) model of computation for modeling and simulation.

The solver layer provides different implementations of solvers (such as linear solver to solve electrical network) that are required to simulate specific AMS descriptions.

The synchronization layer implements a mechanism to organize the simulation of a SystemC-AMS model that may include different continuous-time and discrete event parts. SystemC-AMS defines a generic interface for various continuous-time solvers and provides methods to synchronize analog solvers and the discrete kernel of SystemC.

SystemC AMS extensions are not intended to replace circuit simulators. The use of more accurate circuit simulators to verify circuit implementations can be applied, once an integration of a circuit simulator is available. Advantages of SystemC-AMS SystemC-AMS Flow

The SystemC-AMS simulation cycle is shown in Figure 3 and is summarized below:

Figure 3: SystemC – AMS Simulation Cycle SystemC Applications

5 Modeling Approaches and performance trade-off

The block diagram of different modeling approaches for AMS design is as shown in Figure 4.

Figure 4 : AMS modeling Approaches

Table 1 provides information about the comparison of various parameters for each of the approaches used for AMS systems. The main parameters considered are accuracy, abstraction level, time required for modeling the system, simulation times, tools required and the support.

Parameter  VHDL-AMS  Verilog-A  SystemC-AMS  SPICE
Accuracy Med – High  Med - High  Med - High  High
Abstraction Level  Any abstraction level  Any abstraction level  Any abstraction level  Transistor / Netlist level
Time to model  Less to Medium Less to Medium Less  High
Simulation Run Time  Less Less  Medium - High  High
Tools required  Simulator  Simulator AMS libs with GCC/ Simulators Simulators
Support Available  Available  Less  Available

Table 1: Modeling approaches and performance trade-off.

6 Case study: Digital Phase Locked Loop (DPLL)

This section takes example of the DPLL and explains how a system can be modeled using the available modeling options. A typical DPLL as shown in Figure 5; it consists of four main blocks: a phase detector, a low pass filter, a VCO and a modulo N-bit divider. The actual implementation consists of the phase detector (PD) using XOR gate and a low pass filter (LPF) using a RC network. Each of these components can be modeled using SystemC AMS, VHDL-AMS, Verilog-A and Spice, with respective digital components being modeled either in SystemC, VHDL or Verilog. Table 2 shows the available options for modeling of DPLL.

Figure 5: Block diagram of DPLL

The following table shows various components of DPLL along with available options in which the system can be implemented. Four variants of implementation are available with the available modeling languages and tool set.

Component PD and %N  LPF VCO  Comments
Option 1 SystemC-AMS  SystemC-AMS  SystemC-AMS Using GCC / SystemC AMS libraries
Option 2  VHDL / Verilog  VHDL-A / Verilog-A VHDL-A / Verilog-A  Using EDA – AMS Simulator
Option 3  VHDL / Verilog  Spice  VHDL –A / Verilog-A / Spice  Co-simulation using Spice and EDA simulator
Option 4  VHDL / Verilog Spice  SystemC AMS Co-Simulation if simulator* supports SystemC AMS

Table 2: Various Options to model DPLL

7 Conclusion

The study of various modeling options available for AMS systems provided an opportunity to explore the different architectures with an emphasis on co-simulation and parameters like accuracy, time to model, simulation time etc. It is recommended to use an appropriate approach based on the criticality of parameters and usage of application. For example, SystemC AMS provides a platform for architectural exploration of AMS systems supported by AMS libraries and uses open source tools (like gcc, gdb etc) and less time to model while improving the simulation speed.