Today, ASIC design flow is a very solid and mature process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now.

Each and every step of the ASIC design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly. And most importantly, all the EDA tools can import and export the different file types to help making a flexible ASIC design flow that uses multiple tools from different vendors.

ASIC design flow is not exactly a push button process. To succeed in the ASIC design flow process, one must have: a robust and silicon-proven flow, a good understanding of the chip specifications and constraints, and an absolute domination over the required EDA tools (and their reports!).

This article covers the ASIC design flow in very high level. We will provide a more detailed articles in the future explaining more about the activities within each phase. Let’s start with the first step.

ASIC System Design

Assuming your ASIC specifications are completed and approved by the different parties, it’s time to start thinking about the architectural design. In ASIC system design phase, the entire chip functionality is broken down to small pieces with clear understanding about the block implementation. For example: for an encryption block, do you use a CPU or a state machine. Some other large blocks need to be divided into subsystems and the relationship between the various blocks has to be defined.  In this phase the working environment is documentation.

Register Transfer Level (RTL)

For digital ASICs or for digital blocks within a mixed-signal chip, this phase is basically the detailed logic implementation of the entire ASIC. This is where the detailed system specifications is converted into VHDL or Verilog language. In addition to the digital implementation, a functional verification is performed to ensure the RTL design is done according to the specifications.

When all the blocks are implemented and verified the RTL is then converted into a gate level netlist.

Synthesis

In this phase the hardware description (RTL) is converted to a gate level netlist. This process is performed by a synthesis tool that takes a standard cell library, constraints and the RTL code and produces an gate-level netlist.

Synthesis tools are running different implementations to provide best gate level netlist that meets the constraints. It takes into account power, speed, size and therefore the results can vary much from each other. To verify whether the synthesis tool has correctly generated the gate-level netlist a verification should be done.

Layout

In this stage, the gate level netlist is converted to a complete physical geometric representation. The first step is floorplanning which is a process of placing the various blocks and the I/O pads across the chip area based on the design constraints. Then placement of physical elements within each block and integration of analog blocks or external IP cores is performed. When all the elements are placed, a global and detailed routing is running to connect all the elements together.

Also after this phase a complete simulation is required to ensure the layout phase is properly done.

The file produced at the output of the layout is the GDSII (GDS2) file which is the file used by the foundry to fabricate the silicon. The layout should be done according the silicon foundry design rules.