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Handheld PCs, PDAs and smart cell phones are showing up in new applications every day. These new products are made possible by the adoption of wireless technology and the internet. Taxi and delivery services, vendors at fairs and swap meets and many other mobile merchants are now able to accept credit cards in the field.

Semtek Corp, a San Diego based company that manufactures credit card readers, was developing a new product. “Our new reader had to be small, very low power and low cost,” remarked Dennis Mos, VP Sales and Marketing at Semtek.

Size, power and cost are all benefits of ASIC technology; however, developing an ASIC, particularly a Mixed Signal ASIC, can be expensive and time consuming. Such an undertaking may prove especially risky for new product like Semtek’s wireless credit card reader. Many engineering managers are of the mind that ASIC’s are best left to the “Big Boys.” And considering the high cost of tools, masks and fabrication they are probably correct, but not completely.

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b2ap3_thumbnail_download-2.pngThese days, a typical corner (TT) is no longer typical for most applications. For that matter, standard PVT Corners (FF/TT/SS), generally, do not represent the exact environmental conditions in which an ASIC/SoC will be functioning. This means the voltage may not be a nominal Vdd in a typical case or Vdd±10% in an extreme case; and the temperature may not be 25C in a typical case or 125C/-40C in extreme cases. Also, in today's market, everyµW of power saved, and nS of delay avoided, makes a significant difference in a product's performance and cost. Therefore, it is important to know how a system behaves under real-time PVT conditions. One needs to characterise foundation IPs at these special (custom) corners to avoid overdesign and achieve optimal product for best power and performance. When estimating the power and timing numbers of an IP at a custom corner (e.g., @95C and Vdd+3%), it is not easy to derive values from regular SS, TT, and FF characteristics as these may not support linear extrapolations. Even small errors in calculation can be very risky. One approach is to use characterisation tools (e.g., Silicon Smart from Synopsys) that can easily characterise foundation IPs to estimate power and performance of an SoC at any custom corner with substantial accuracy using reference ".lib" files.

Ensuring accuracy

In order to generate an accurate custom corner ".lib" file, one must ensure that a reference ".lib" file, which is already provided by an IP vendor, can be generated using the setup. The better co-relation achieved ensures more accurate ".lib" generation for the custom corner. Various options and settings available in the tool enable proper alignment of setup to adhere to the processes followed by different vendors to generate highly accurate ".lib" files. The tool also provides the flexibility to choose between different simulator environments available in the market (e.g., HSpice, Spectre).

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Simulink models are used as executable specifications in commonly used design flows for mixed-signal ASICs. Based on these specifications, analog and digital components are directly implemented in mixed-signal design environments. This step constitutes a large leap of abstraction. In this work, we address this aspect by showing and discussing an approach for automated transitions from Simulink models representing analog and digital components to HDL descriptions using HDL Coder. On the one hand, we translate analog Simulink components into continuous-value discrete-time HDL descriptions that can serve as reference behavioral models in the mixed-signal design environment. On the other hand, for digital Simulink components, we developed optimizations for Simulink models in order to achieve resource-efficient HDL descriptions. Both solutions in the analog and digital domain were integrated into Simulink Model Advisor. An evaluation of the presented design flow, as applied to an automotive hardware design, is shown.

Electronic Control Units (ECUs) in the field of automotive electronics generally interact with the physical environment by using sensors and actuators. Thereby, mixed-signal ASICs (Application Specific Integrated Circuits) are needed as an interface between microcontrollers and sensors as well as actuators. In this work, we focus on ASICs connected to sensors, whereby the sensor is often enclosed with the ASIC into a system-in-package (SiP). In the most general case, mixed-signal ASICs consist of analog, non-programmable digital and programmable digital components.

The increasing integration density of ASICs allows more and more functionality, which leads to more complex ASIC designs. These require a holistic view on a high abstraction level at the beginning of the design. Therefore, a system-level (SL) design methodology is needed, where all ASIC components and the associated sensor are modeled in a common SL design environment. In standard flows, the design starts by developing an SL model that serves as executable functional specification. Based on this specification, the particular ASIC components are designed on implementation level (IL) isolated from the overall system and without any reuse of the design effort performed at SL. The isolation between SL and IL constitutes a gap in the design flow, which leads to redundant implementation efforts and consistency problems between SL and IL. Furthermore, the isolation of components from the overall system during implementation leads to lost optimization potential. That is why in (1), we proposed a seamless SL design methodology, which uses automated transitions from SL to IL models in order to reduce the effort of design transfer between SL and IL (see Figure 1).

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